This invention relates to a semiconductor integrated circuit device and also to a manufacturing technique thereof. More particularly, the invention relates to an effective technique for application to the formation of a copper (Cu) wiring by use of a Damascene method.
In recent years, with a reduction in the scale of wirings resulting from the high degree of integration of an LSI, the wiring resistance has increased significantly. Especially, with a high-performance logic LSI, an increase in the wiring resistance has become one of the great factors impeding realization of an increased high performance.
To cope with this, a buried Cu wiring has now been brought in by use of the so-called Damascene method, wherein a groove for wiring is formed in an interlayer insulating film on a silicon substrate and a Cu film is deposited over the interlayer insulating film, including the inside of the wiring groove, and this is followed by removing the unnecessary portion of the Cu film disposed outside of the wiring groove by use of a chemical mechanical polishing (CMP) method. Along with the reduction of the wiring resistance by the introduction of the above Cu wiring, the introduction of an interlayer insulating film using, for example, SiOF, whose dielectric constant is lower than that of a silicon oxide film, has been adopted from the standpoint of reducing the capacitance of the wiring.
Japanese Laid-open Patent Application No. Hei 2000-277520 discloses a technique of forming a buried Cu wiring, according to the Damascene method, inside a wiring groove formed in an interlayer insulating layer made of SiOF. An outline of this technique will be described below.
Initially, a silicon oxide film is deposited on a silicon substrate on which a transistor has been formed, and an SiOF film is subsequently deposited on the silicon oxide film through an etching stopper film. The etching stopper film on the silicon oxide film is used to prevent the lower silicon oxide film from being etched upon the formation of a groove for wiring by dry etching of the SiOF film. This etching stopper film is constituted of a material that is unlikely to be etched with the gas used for etching the SiOF film, e.g. a silicon nitride film or a silicon oxynitride (SiON) is used for this purpose.
Next, a groove for wiring is formed in the SiOF film by dry etching through a mask formed by a photoresist film. After formation of a thin barrier film and a sputtered Cu film over the SiOF, film including the inside of the wiring groove, a thick Cu film is further deposited thereon by an electroplating method or the like. The barrier film is formed so as to prevent the Cu in the wiring groove from being diffused into the SiOF film, thereby not adversely influencing the element characteristics. In this application, the barrier film is formed of a material that has good bonding to the SiOF film in order to prevent separation thereof at the interface with the SiOF film, e.g. the barrier film is constituted, for example, of tantalum nitride (TaN) having a nitrogen content of 30 to 60%. The sputtered Cu film functions as a seed film when a Cu film is grown according to an electroplating method. Next, an unnecessary portion of the Cu film, the sputtered Cu film and the barrier film on the SiOF film are removed by a chemical mechanical polishing method to form a Cu wiring inside the wiring groove.